SmartDV’s Ethernet Cyclic FEC IP is a silicon-proven, fully featured Forward Error Correction solution purpose-built for SoC designs requiring reliable backplane and copper cable signal integrity across 10GBASE-R, 25GBASE-R, 40GBASE-R, 50GBASE-R, and 100GBASE-R Ethernet PHY applications. Fully compliant with IEEE 802.3 Clause 74 BASE-R FEC, it delivers complete cyclic error correction functionality implementing the (2112,2080) binary cyclic code, shortened from the cyclic Fire code (42987,42955), with 32 parity bits providing coding gain to increase link budget and bit error rate performance between the PCS and PMA sublayers.
Designed to address the burst-error characteristics common to backplane and copper cable channels, the IP corrects burst errors of up to 11 bits within each 2112-bit codeword, operating autonomously on a per-PCS-lane basis for multi-lane BASE-R PHYs. Its pipelined error correction architecture, bit locking mechanism, and full alignment, transcoding, and scrambling functions performed within the core give networking SoC teams a production-tested, spec-complete Firecode FEC implementation suited for 10G through 100G backplane and copper cable interconnect designs.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean host interface enable fast integration across a wide range of networking process nodes.
