SmartDV’s Ethernet 1.6T PCS IP is a next-generation Physical Coding Sublayer solution purpose-built for SoC designs requiring the highest available Ethernet bandwidth for AI accelerator, GPU interconnect, and hyperscale data center backbone applications. Targeting the IEEE 802.3dj specification, it delivers 1.6 Terabit PCS functionality built on 224G PAM4 SerDes lane technology, doubling the per-lane speed of IEEE 802.3df 800G Ethernet while reusing proven PAM4 modulation, Gray coding, and pre-coding techniques from earlier high-speed Ethernet generations.
Designed for the extreme bandwidth demands of AI training clusters and next-generation data center interconnects, the IP implements 8-lane PCS architecture at 224 Gbps per lane, symbol-multiplexed FEC architecture that contains burst errors within fewer symbols for improved FEC effectiveness compared to 800G bit-multiplexing approaches, concatenated FEC for enhanced error correction, and support for chip-to-module and chip-to-chip attachment unit interfaces. Its alignment with 800GBASE-DR4 and 1.6TBASE-DR8 optical reach profiles gives hyperscale and AI infrastructure SoC teams an early, forward-looking PCS implementation for the emerging 1.6T Ethernet ecosystem.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized lane architecture and clean host interface enable fast integration across a wide range of advanced process nodes and target applications.