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DisplayPort 2.x Receiver IP
Design IP
Overview

SmartDV’s DisplayPort 2.x Receiver IP is a silicon-proven, high-performance solution built to support next-generation display and video applications across consumer electronics, computing, and embedded systems. Fully compliant with VESA DisplayPort 2.0 and 2.1 specifications, it supports ultra-high bandwidth, multi-stream transport (MST), and enhanced video resolutions, including 8K and beyond, while ensuring robust data integrity and low latency.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. Its advanced feature set includes support for Display Stream Compression (DSC), Forward Error Correction (FEC), and Adaptive Sync, making it an ideal choice for high-resolution, high-refresh-rate display applications.

DisplayPort Receiver
Benefits
  • Next-Gen Standards Compliance – Supports full receiver functionality as per VESA DisplayPort 2.0 and 2.1 specifications, including Main Link, AUX Channel, and Hot Plug Detect (HPD)
  • Ultra-High Bandwidth Readiness – Supports all UHBR rates: UHBR10, UHBR13.5, and UHBR20 with dynamic lane configurations (1, 2, or 4 lanes) and parallel data widths of 10, 20, 40, or 80 bits
  • Flexible Video Interface – Accommodates 1, 2, 4, or 8 pixels per clock with support for interlaced and progressive video streams across various formats
  • Comprehensive Format Support – Processes RGB, YCbCr (4:4:4, 4:2:2, 4:2:0), Y-only, and RAW video formats with up to 48 bits per pixel
  • Full Secondary Data Packet Handling – Supports Audio Stream, Audio Timestamp, VSC, InfoFrames, Camera SDP, PPS, ISRC, Adaptive Sync, and all other SDP formats
  • Advanced Protocol Features – Includes Main Stream Attribute (MSA) packet handling, Enhanced and Default Framing Modes, nibble interleaving (ECC), TPS2–TPS4 training patterns, and Horizontal Blanking Expansion
  • Efficient and Adaptive Integration – Supports SST and MST modes with Split SDP, I2C-over-AUX with EDID, and DPCD register access
  • Secure Content Ready – Compatible with HDCP 2.3 for encrypted content streams, supporting both full authentication and bypass modes
Compliance and Compatibility
  • Compliant with VESA DisplayPort 2.1 specification and backward compatible with 1.4a and earlier versions
  • Optional support for Display Stream Compression (DSC) 1.2a and HDCP up to version 2.3, including support for authentication bypass
  • Compliant with Forward Error Correction (FEC) using RS(254,250) for UHBR link robustness
  • Compatible with both ANSI 8b/10b and 132b/128b channel encoding and decoding schemes
  • Compatible with all major EDA synthesis, simulation, and linting flows