SmartDV’s CXPI Slave IP is a fully featured Clock Extension Peripheral Interface slave solution purpose-built for automotive peripheral SoC designs requiring reliable, deterministic slave-side participation in CXPI networks across body electronics, HMI, lighting, door control, and other cost-sensitive automotive subsystems. Fully compliant with ISO 20794, it delivers complete slave-side CXPI functionality supporting both Event Trigger and Polling bus access methods at data rates up to 20 kbps over a single-wire bus, synchronized to the master-distributed clock — providing a feature-complete CXPI slave implementation for automotive peripheral and sensor SoC designs.
Designed for the demanding requirements of modern automotive body network peripheral designs, the IP synchronizes to the master-provided clock, participates in CSMA/CR collision resolution for event-triggered transmissions, responds to polling schedule requests from the master, and supports both NRZ and PWM data encoding modes. Its 8-bit CRC for normal frames and 16-bit CRC for long frames, automated retransmission, wakeup pulse generation and detection, programmable clock frequency up to 100 MHz, and 128x bit time oversampling give automotive peripheral SoC teams a spec-complete CXPI slave implementation suited for the most demanding body network sensor and actuator applications.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its single-wire implementation, low-cost architecture, and clean host interface enable fast integration and confident design bring-up across a wide range of automotive process nodes and target applications.
