SmartDV’s CXPI Master IP is a fully featured Clock Extension Peripheral Interface master solution purpose-built for automotive SoC designs requiring reliable, deterministic master-side control of CXPI networks across body electronics, HMI, lighting, door control, and other cost-sensitive automotive subsystems. Fully compliant with ISO 20794, it delivers complete master-side CXPI functionality supporting both Event Trigger and Polling bus access methods at data rates up to 20 kbps over a single-wire bus, with clock distribution to all connected slave nodes and support for up to 16 nodes per network.
Designed for the demanding requirements of modern automotive body network designs, the IP provides clock generation and distribution to the CXPI bus, manages bus access via CSMA/CR collision resolution for event-triggered frames and polling schedules for periodic data, and supports both NRZ and PWM data encoding modes. Its 8-bit CRC for normal frames and 16-bit CRC for long frames, automated retransmission, wakeup pulse generation and detection, programmable clock frequency up to 100 MHz, and 128x bit time oversampling give automotive SoC teams a spec-complete CXPI master implementation suited for the most demanding body network control applications.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its single-wire implementation, low-cost architecture, and clean host interface enable fast integration and confident design bring-up across a wide range of automotive process nodes and target applications.
