CXL 3.x Controller IP

Design IP

Overview

SmartDV’s CXL (Compute Express Link) 3.x Controller IP brings high-speed, coherent connectivity with enhanced fabric capabilities—supporting memory-centric architectures and disaggregated compute environments at scale. Fully compliant with the CXL 3.x specification, it introduces features such as multi-level switching, memory sharing across multiple hosts, and support for global fabric-attached memory.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. SmartDV’s CXL 3.x IP supports backward compatibility with CXL 1.x and 2.0, includes advanced security features, and offers robust scalability for building memory fabrics and dynamic topology-aware systems in modern data centers.

Benefits

Fabric-Based Coherency – Supports CXL 3.0 memory-centric architecture with enhanced coherency, peer-to-peer communication, and fabric capabilities
High-Speed Performance – Built on PCIe Gen6, supporting 64 GT/s signaling and FLIT-based data transmission for reduced latency and higher bandwidth
Memory Sharing & Pooling Enhancements – Enables multi-level switching, memory sharing across multiple hosts, and dynamic resource allocation
Protocol and Topology Flexibility – Supports CXL.io, CXL.cache, CXL.mem, and new fabric protocols with support for broadcast, multicast, and device fanout
Advanced Virtualization Support – Designed for disaggregated systems with support for global fabric IDs, fabric-attached devices, and scalable memory hierarchies
Robust Error Handling – Implements advanced framing error detection, CXL Error VDMs, and telemetry features for end-to-end visibility and diagnostics
High Integration Scalability – Supports up to 4K payloads, 256 functions, expanded virtual channel management, and dynamic address translation
Optimized for Complex SoCs – Fully supports Type 1, 2, and 3 devices with enhanced cache coherency and memory access across fabric nodes

Compliance and Compatibility

Fully compliant with CXL 3.0 and 3.1 specifications
Built on PCI Express Base Specification 6.0 with FLIT mode
Compatible with all major EDA synthesis, simulation, and linting flows

Related Products

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PCIe 6.0 Controller IP

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