CXL 2.x Controller IP

Design IP

Overview

SmartDV’s CXL (Compute Express Link) 2.0 Controller IP extends support for advanced memory pooling, switching, and persistent memory, enhancing scalability and resource efficiency for high-performance computing, AI, and cloud infrastructure. Fully compliant with the CXL 2.0 specification, it enables dynamic resource sharing through support for memory and device disaggregation over a common PCIe infrastructure.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. With features like IDE (Integrity and Data Encryption), enhanced fabric management, and dynamic device enumeration, SmartDV’s CXL 2.0 Controller IP is ideal for next-gen heterogeneous systems requiring secure and flexible connectivity.

Benefits

High-Performance Coherency Architecture – Implements Compute Express Link (CXL) 2.x protocol supporting CXL.io, CXL.cache, and CXL.mem for high-speed CPU–device and device–device communication
Scalable Memory Expansion – Enables memory pooling and sharing with advanced memory coherency between host and accelerators
Flexible Configuration – Supports root-complex, device, and switch port configurations for a range of SoC integration needs
Low-Latency Data Path – Optimized pipeline architecture ensures minimal transaction latency and high throughput across PCIe 5.0/6.0 PHY interfaces
Robust Error Handling – Includes link- and transaction-layer error detection, reporting, and recovery mechanisms
Security and Reliability – Optional ECC protection and parity checks for command and data integrity
Seamless Integration – Designed for easy adoption with standard bus interfaces such as AXI and TileLink, and compatible with PCI Express controller frameworks

Compliance and Compatibility

Fully compliant with CXL 2.0 and 2.1 specifications
Aligns with PCI Express 5.0 and 6.0 specifications for underlying PHY connectivity
Compatible with all major EDA synthesis, simulation, and linting flows

Related Products

CXL (1.1/2.0/3.0) VIP

CXL 3.x Controller IP

PCIe 5.0 Controller IP

PCIe 6.0 Controller IP