SmartDV’s Camera Link HS Verification IP is a comprehensive solution for verifying the Camera Link HS interface, a high-bandwidth machine vision standard designed for industrial imaging applications requiring fast, reliable data transmission between cameras and frame grabbers. Fully compliant with Camera Link HS v1.2 and backward compatible with v1.0 and v1.1, it supports complete verification of Camera Link HS Transmitter and Receiver devices across M-Protocol at 3 Gbps with 8B/10B encoding and X-Protocol at 10 Gbps and 25 Gbps with 64B/66B encoding and Forward Error Correction, covering all message packet types, pixel formats, bit depths, and packetization configurations of up to 8 cables with up to 15 data lanes per cable.
SmartDV’s Camera Link HS VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With support for all seven pulse trigger modes, 32 GPIO, comprehensive color format coverage in both Mixed and Planar data presentations, GenCP v1.1 command messaging, packet interruption based on message priority, Ack/Nack/Resend handshaking, device control register verification, built-in functional coverage, and a complete test suite, SmartDV’s Camera Link HS VIP enables verification teams to thoroughly validate machine vision interface designs for industrial inspection, scientific imaging, defense, and high-performance embedded vision applications.
