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Camera Link HS Frame Grabber IP
Design IP
Overview

SmartDV’s Camera Link HS Frame Grabber IP is a high-performance solution designed to interface with high-speed industrial and scientific imaging systems. It supports reliable, low-latency data capture from Camera Link HS transmitters, making it ideal for applications requiring precision and throughput, such as machine vision, automated inspection, medical imaging, and high-speed recording.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. It offers seamless integration with Camera Link HS protocols, including support for multiple data lanes, low-skew clock recovery, and robust error detection, ensuring accurate and efficient image acquisition in demanding environments.

Benefits
  • Full CLHS Receiver Functionality – Compliant with Camera Link HS specification up to v1.1, supporting full frame grabber feature set
  • Robust Messaging & Control Support – Handles Video, Command, Acknowledge, Revision, and all 7 trigger pulse modes, with Ack/Nack/Resend
  • Flexible Video Format Support – Supports 8, 10, 12, 14, and 16-bit depth with raw, mono, RGB, BGRa, and Bayer pattern inputs
  • Scalable Cable & Lane Architecture – Receives data over up to 8 cables, each supporting up to 15 data lanes for maximum bandwidth
  • Protocol Versatility – Supports both M-Protocol (3 Gbps, 8B/10B encoding) and X-Protocol (10 Gbps, 64B/66B with FEC)
  • Mixed and Planar Color Support – Handles color pixel formats in both Mixed and Planar configurations for broad compatibility
  • Intelligent Packet Handling – Supports prioritized packet reception and interruption for real-time responsiveness
  • GenCP & Register Set Support – Supports GenCP v1.1-based command message parsing and CLHS v1.1-compliant device control registers
Compliance and Compatibility
  • Fully compliant with Camera Link HS specification up to v1.1
  • Supports GenCP v1.1 command message parsing and CLHS-compliant receiver register map
  • Compatible with all major EDA synthesis, simulation, and linting flows