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Overview

SmartDV’s ARINC 429 Verification IP is a comprehensive solution for verifying the Mark 33 Digital Information Transfer System bus, the predominant avionics data bus standard used across commercial and transport aircraft. Fully compliant with ARINC Specification 429 Part 1-18, it supports complete verification of ARINC 429 transmitters and receivers across simplex twisted shielded pair data bus configurations, covering all word structures, protocol requirements, data types, and transmission rates, with support for LRUs containing multiple transmitters and receivers communicating across independent buses.

SmartDV’s ARINC 429 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With support for all ARINC 429 data types including BNR, BCD, Discrete, Maintenance Data and Acknowledgement, and Williamsburg/Buckhorn Protocol, both low and high speed transmission rates, bipolar Return-to-Zero encoding, comprehensive error injection and detection, glitch injection, built-in functional coverage, and a complete test suite, SmartDV’s ARINC 429 VIP enables verification teams to thoroughly validate avionics data bus designs for commercial aviation, defense, and aerospace applications.

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ARINC 429 VIP
Benefits
  • Full Transmitter and Receiver Support – Supports complete ARINC 429 source and sink operation with LRU configurations containing multiple transmitters and receivers communicating on independent buses, programmable FIFO depth, and a rich set of configuration parameters for fine-grain protocol control.
  • Complete Word Structure and Protocol Coverage – Supports all 32-bit ARINC 429 word structures comprising a 24-bit data portion and an 8-bit label, all protocol requirements for bus communication as per specification, and all word format variants as defined in ARINC 429 Part 1-18.
  • All Data Type Support – Covers Binary (BNR) in fractional two’s complement notation, Binary Coded Decimal (BCD) as a numerical subset of ISO Alphabet No. 5, Discrete Data combining BNR, BCD, and individual bit representations, Maintenance Data and Acknowledgement with two-way duplex communication between source and sink, and Williamsburg/Buckhorn Protocol for bit-oriented file transfers.
  • Dual Speed Transmission Support – Supports low speed operation at 12.5 kHz with an allowable range of 12 to 14.5 kHz, and high speed operation at 100 kHz with ±1% tolerance, with bipolar Return-to-Zero encoding and decoding across both transmission rates.
  • Comprehensive Error Injection and Detection – Supports injection and detection of all ARINC 429 error types including missing SOT word, LDU Sequence Number errors, parity errors, word count errors, CRC errors, and timeout errors, along with glitch injection and detection for physical layer verification.
  • Complete Verification Infrastructure – Provides built-in functional coverage analysis, constraints randomization, status counters for bus events, and callbacks in source and sink for user-defined event handling and protocol and timing violation notification.
Compliance and Compatibility
  • Fully compliant with ARINC Specification 429 Part 1-18; backward compatible with Part 1-17 and earlier revisions
  • Supports Williamsburg/Buckhorn Protocol for file data transfer as defined in ARINC 429 Part 3
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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