SmartDV’s APB Multilayer Interconnect IP is a silicon-proven, high-performance AMBA APB bus fabric solution purpose-built for SoC designs requiring flexible, multi-master peripheral bus interconnect across embedded processor, IoT, and low-power domain designs. Fully compliant with the AMBA APB5 specification, it supports up to 16 masters and 16 slaves with per-slave round-robin or priority-based arbitration, user-defined slave-to-master mapping, and arbitration performed at each slave port, delivering higher throughput and lower arbitration overhead compared to centralized APB bus designs.
Designed for the practical integration requirements of modern multi-master APB SoC designs, the IP provides a standardized user interface for easy integration with any IP, control logic mapping user interface signals to APB signals, configurable data and address bus widths, user-defined slave address mapping per master, and support for all APB protocol transfer types and response types including protected accesses and write strobe. Its configurable endianness and response generation with wait states give SoC peripheral bus teams a production-tested, feature-complete APB multilayer fabric.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized master and slave count, configurable arbitration scheme, and clean integration interface enable fast design bring-up across a wide range of process nodes and target applications.
