SmartDV’s AMBA ACE AIP is a fully featured SVA-based formal verification IP purpose-built for SoC designs requiring exhaustive, property-driven verification of AMBA ACE coherency protocol compliance across cache-coherent interconnect, CPU subsystem, and multi-master SoC designs. Covering ACE, ACE-Lite, ACE5-Lite, ACE5-LiteDVM, and ACE5-LiteACP interface classes, it delivers a comprehensive set of SystemVerilog Assertions targeting the full breadth of ACE protocol rules including transaction ordering, coherency state machine correctness, snoop response compliance, barrier semantics, and cache maintenance operation sequencing.
Designed to complement simulation-based verification with the exhaustive state space exploration that only formal methods can provide, the AIP targets the class of subtle coherency bugs including illegal state transitions, ordering violations, snoop filter inconsistencies, and barrier sequencing errors that are statistically unlikely to surface in directed or constrained-random simulation but can cause catastrophic system failures in silicon. Its parameterized constraint and assumption architecture allows formal tools to focus verification effort on the most critical protocol properties while bounding the state space to tractable problem sizes.
Compatible with industry-standard formal verification tools and fully independent of any specific EDA vendor platform, the AIP integrates cleanly into existing formal flows with minimal setup overhead. Its modular property organization, configurable protocol parameters, and clear assertion naming conventions enable verification teams to rapidly deploy, customize, and extend the property set to match the specific ACE configuration and design context of their SoC.
