SmartDV’s AFDX 1G End-System IP is a silicon-proven, fully featured Avionics Full-Duplex Switched Ethernet end-system solution purpose-built for safety-critical avionics and aerospace SoC applications requiring complete AFDX network node implementation. Fully compliant with ARINC 664 Part 7 and IEEE 802.3-2018, it delivers a complete end-system implementation supporting full-duplex Ethernet at 10/100/1000 Mbps with integrated PHY management via MDIO, Virtual Link traffic shaping, and comprehensive TSN feature support — providing a proven, production-ready AFDX end-system foundation for next-generation avionics network designs.
As a complete end-system implementation rather than a standalone MAC, the IP integrates MDIO Clause 22 and Clause 45 PHY management alongside the full AFDX MAC feature set including Virtual Link Bandwidth Allocation Gap enforcement, frame replication and elimination, traffic scheduling, class-based flow control, and cut-through support. Its comprehensive TSN feature set, detailed per-Virtual-Link statistics, and independently configurable TSN features give avionics SoC teams a production-tested, spec-complete AFDX end-system that meets the stringent determinism and reliability requirements of DO-178C and DO-254 certified avionics designs.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its fully synthesizable architecture, GMII/RGMII/MII physical interface support, and AXI4 Stream packet data interface enable fast integration and confident design bring-up across a wide range of avionics process nodes and target applications.
