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Author: Kathleen Ardner

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IP Your Way: Why Customizable IP Is Essential for Modern SoC Design

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SmartDV以定制IP和生态合作闪耀ICCAD 2024

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Joining SmartDV: A Journey of Growth and Collaboration

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Field Notes from Embedded World 2024

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A Deeper Dive into IP Core Considerations for Safety-Critical Applications

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Customization is Key: Field Notes from the 2023 RISC-V Summit

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Sourcing IP for Safety-Critical SoCs

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中国芯,寻找新赛道迫在眉睫 (China Core Finding a New Track)

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My Cheesy Must-See List for DAC 2023

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IP Industry Transformation

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How Memory Models Improve DDR and SoC Verification Accuracy

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DDR Verification Challenges in Modern Chip Design

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SmartDV and Mirabilis Design Announce Strategic Collaboration for System-Level Modeling of SmartDV IP

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SmartDV Announces Multiple Customer Licenses for MIPI® SoundWire® I3S℠ 1.0 IP Portfolio

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SmartDV Introduces Advanced H.264 and H.265 Video Encoder and Decoder IP

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SmartDV Licenses SDIO IP Family to RANiX for V2X Products

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SmartDV Taps MosaIC for IP Sales Representation in Israel

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SmartDV Redoubles Focus on Customer Experience and IP Your Way

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SmartDV Rolls Out Multi-Phase Expansion Plan

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Codasip Partners with SmartDV to Accelerate Chip Design Projects

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SmartDV Achieves ISO 9001:2015 Certification

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UVM Testbench Architecture & Verification IP (VIP) Integration

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What Is Verification IP and Why It Matters in Modern SoC Design