Deepak Kumar Tala, CEO, SmartDV
EEWeb
April 10, 2019
Chip design teams employ Verification IP to improve quality, reduce the risk of silicon re-spins, accelerate project delivery, and increase ROI.
Verification engineers have a difficult task — ensuring the functional correctness of increasingly complex SoC designs filled with integrated blocks of IP, many based on sophisticated industry-standard protocols.
The lengthy verification process typically involves simulation- or hardware-emulation–based techniques built around a testbench with stimulus generators, scoreboards, checkers, and functional coverage models.
Yet functional bugs continue to escape, becoming a major cause of costly silicon re-spins. Achieving full verification closure has never been more challenging.
Verification IP (VIP) provides relief by offering reusable functional blocks that support industry-standard interfaces and accelerate verification sign-off. VIP strengthens the verification environment, improves debug and coverage closure, and shortens project schedules by giving teams a trusted reference model against which designs can be compared.
Typically delivered as compliant, plug-and-play modules in languages such as UVM, SystemVerilog, or SystemC, Verification IP is not a verification methodology itself but a critical component within one.
VIP helps verify system-level functionality and validate performance by generating application-specific traffic. Complex SoCs require multiple VIPs to generate comprehensive tests and verify various interfaces and protocols. A complete VIP includes sequences, drivers, configuration components, test plans, and test suites to interact with the DUT in simulation or emulation.
Third-party VIP vendors often participate in standards bodies and bring unmatched domain expertise. Their cores are production-proven, fully compliant, and supported by robust functional coverage. For emulation and FPGA prototyping, VIP is delivered as synthesizable RTL with a compatible API for seamless migration from simulation. These vendors also help identify hard-to-find bugs, accelerate run times, and support customization needs.
With verification consuming up to 70% of a project timeline, Verification IP is now an essential part of modern verification strategy — improving quality, reducing re-spin risk, accelerating schedules, and increasing ROI.