Ultra Ethernet VIP

Simulation

Key Features Compliance and Compatibility

Overview

SmartDV’s Ultra Ethernet Verification IP is a comprehensive solution for verifying Ultra Ethernet, the Ultra Ethernet Consortium’s open, Ethernet-based communication architecture purpose-built for scale-out AI and High-Performance Computing networking across NICs, switches, optics, and cables. Fully compliant with UEC Specification 1.0.1, it supports complete verification of Ultra Ethernet endpoints implementing the Ultra Ethernet Transport (UET) protocol, modern RDMA for Ethernet and IP, and the standard physical layer supporting QSFP-DD and OSFP optics, built on the globally adopted Ethernet standard for low-friction, multi-vendor interoperable deployment.

SmartDV’s Ultra Ethernet VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With receiver-driven congestion control, packet spraying across all available network paths, JobID-based job initialization and fabric endpoint mapping, Libfabric UET Provider software architecture support, comprehensive error injection, built-in functional coverage, and a complete test suite, SmartDV’s Ultra Ethernet VIP enables verification teams to thoroughly validate Ultra Ethernet interface designs for AI training and inference clusters, HPC fabrics, hyperscale data center networks, and any scale-out interconnect requiring open, standards-based, vendor-neutral high-performance Ethernet.

Key Features

Full Ultra Ethernet Endpoint Support – Provides complete verification of Ultra Ethernet endpoint behavior implementing the Ultra Ethernet Transport (UET) protocol over standard Ethernet physical layer supporting QSFP-DD and OSFP optics, covering the complete eight-domain architecture spanning physical, link, transport, software, storage, compliance, management, and performance/debugging layers.
Modern RDMA and Transport Coverage – Supports modern RDMA implementations for Ethernet and IP delivering low-latency transport for high-throughput environments, with UET designed to operate without requiring a lossless network, covering reliable and unreliable transport semantics appropriate for distributed AI training and inference workloads.
Receiver-Driven Congestion Control – Supports verification of UEC’s receiver-driven congestion control model, where the receiver actively limits sender transmissions rather than relying on passive network-side congestion signaling, along with packet spraying across all available fabric paths for improved network utilization and reduced tail latency.
Software Stack Integration Coverage – Supports verification aligned with the Libfabric UET Provider software architecture, JobID assignment at job initialization time, and UET Control API JobID mapping and unmapping request structures for complete software-to-hardware integration verification.
Scalable Fabric Architecture Coverage – Supports verification of state maintained only for the duration of active transactions rather than persistent hardware-bound endpoint state, enabling large-scale fabric verification without requiring new switching infrastructure, consistent with UEC’s design for scaling to millions of endpoints.
Comprehensive Error Injection and Detection – Provides automated error injection across physical, link, and transport layers, with checkers verifying protocol timing and functional accuracy at each layer for thorough Ultra Ethernet robustness and fault tolerance verification.
Complete Verification Infrastructure – Provides a full test suite covering all UEC Specification 1.0.1 features, built-in functional coverage analysis, and comprehensive notification of significant events including transactions, warnings, timing, and protocol violations.

Compliance and Compatibility

Compliant with UEC Specification 1.0.1 (Ultra Ethernet Consortium, Linux Foundation)
Supports Ultra Ethernet Transport (UET) protocol over standard Ethernet physical layer
Supports QSFP-DD and OSFP optical interface compatibility
Supports Libfabric UET Provider software architecture integration
Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator