SmartDV’s UART Synthesizable Transactor is a fully featured Universal Asynchronous Receiver/Transmitter bus model purpose-built for hardware emulation and FPGA prototyping environments requiring fast, accurate, and highly configurable UART transmit and receive behavior during pre-silicon validation of embedded, automotive, IoT, and industrial SoC designs. Compatible with the industry-standard UART NS16550A specification, it delivers complete full-duplex UART functionality with programmable baud rates from 110 bps to 1 Mbps, configurable character widths from 1 to 32 bits, and support for Character Mode, FIFO Mode, and Extended FIFO Mode, giving validation teams a drop-in synthesizable UART transactor ready for rapid integration into emulation and prototyping flows.
Designed for the speed and visibility demands of emulation and FPGA prototyping rather than ASIC tape-out, the transactor emphasizes fast bring-up, fine-grained controllability, and on-the-fly protocol checking over area or power optimization. It supports programmable word length, stop bits from 1 to 4.5, and parity configuration, comprehensive error detection covering parity, framing, and overflow errors, full modem control interface with CTS, RTS, DSR, DTR, RI, and DCD signals, programmable hardware flow control, line break detection and generation, and configurable receive FIFO depth, enabling validation teams to exercise corner-case UART behavior that is difficult to reach with production RTL alone.
Built for fast compile times and efficient resource utilization on hardware emulation and FPGA prototyping platforms, the transactor is fully synthesizable and platform-independent, deployable on any hardware emulation or FPGA prototyping platform. Its automatic data formatting, comprehensive interrupt management, and testbench notification of significant events, warnings, timing, and protocol violations enable rapid deployment for early software bring-up and serial communication system-level validation regardless of the underlying emulation platform.
