UALink VIP

Simulation

Benefits Compliance and Compatibility

Overview

SmartDV’s UALink Verification IP is a comprehensive solution for verifying Ultra Accelerator Link, the open industry standard scale-up interconnect developed by the UALink Consortium for low-latency, high-bandwidth accelerator-to-accelerator and accelerator-to-switch communication in AI computing pods. Fully compliant with the UALink 200G 1.0 Specification and the UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0, it supports complete verification of UALink Originator and Completer components implementing the UPLI (UALink Protocol Layer Interface), Transport Layer (TL) Flit conversion, and Data Link (DL) Layer, across x1, x2, and x4 lane Link configurations grouped into Stations delivering up to 800 Gbps per direction.

SmartDV’s UALink VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With support for read, write, and atomic memory-semantic transactions, UALink Switch (ULS) topology with up to 1,024 accelerators per pod, 10-bit accelerator routing identifiers, Virtual Pod partitioning, built-in functional coverage, and a complete test suite, SmartDV’s UALink VIP enables verification teams to thoroughly validate UALink interface designs for AI accelerators, GPUs, scale-up switches, and any data center infrastructure requiring open-standard, multi-vendor accelerator pod interconnect.

Benefits

Full UALink Originator and Completer Support – Provides complete UALink Originator and Completer component verification implementing the UPLI Originator and Completer interfaces, Transport Layer conversion of protocol channels into TL Flits, and Data Link Layer transport, covering the complete symmetrical transmit and receive protocol stack.
Memory-Semantic Transaction Coverage – Supports read, write, and atomic transaction types for accelerator-to-accelerator communication, providing a simple load/store memory-semantic protocol model for direct verification of AI accelerator scale-up data movement.
Lane and Station Configuration Coverage – Supports x1, x2, and x4 lane Link configurations grouped into Stations delivering up to 800 Gbps in each transmit and receive direction, with per-lane data rates of 200 GT/s and 212.5 GT/s signaling rate accounting for Forward Error Correction overhead, based on the IEEE P802.3dj 200G Ethernet physical layer.
Pod Topology and Routing Coverage – Supports UALink Switch (ULS) topology connecting up to 1,024 accelerators per pod, 10-bit unique accelerator routing identifiers, and Virtual Pod partitioning for traffic isolation between non-overlapping subsets of switch ports.
Extended Capability Coverage – Supports verification scope aligned with the UALink Common Specification’s In-Network Compute capability for accelerator-to-accelerator computation and communication, Chiplet Definition for chiplet-based SoC integration, and Manageability features using standardized protocols and APIs.
Complete Verification Infrastructure – Provides a full test suite covering all UALink 200G 1.0 and DL/PL 2.0 specification features, built-in functional coverage analysis, and comprehensive notification of significant events including transactions, warnings, timing, and protocol violations.

Compliance and Compatibility

Compliant with UALink 200G 1.0 Specification (UALink_200 Rev 1.0, April 2025)
Compliant with UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0
Supports x1, x2, and x4 lane Links at 200 GT/s per lane (800 Gbps per Station)
Supports up to 1,024 accelerators per pod via UALink Switches
Based on IEEE P802.3dj 200G Ethernet PHY layer
Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator