SmartDV’s TS5 Verification IP is a comprehensive solution for verifying the JEDEC fifth-generation Temperature Sensor interface, the two-wire serial bus thermal sensor standard used in DDR5 memory modules, SSDs, computing motherboards, and communications equipment requiring real-time, closed-loop thermal management. Fully compliant with JEDEC TS5 (JESD302-1A, TS511X and TS521X Serial Bus Thermal Sensor Device Standard), it supports complete verification of TS5 Master and Slave components across I2C and I3C two-wire serial bus operation, transfer rates up to 15 MHz, two unique device addresses selected by the SA pin, START, repeat START, and STOP sequencing, and START byte generation and handling.
SmartDV’s TS5 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With master/slave arbitration and clock synchronization, in-band interrupts, parity error checking, packet error checking, device read address pointer mode, comprehensive error injection, built-in functional coverage, and a complete test suite, SmartDV’s TS5 VIP enables verification teams to thoroughly validate TS5 thermal sensor interface designs for DDR5 DIMM and RDIMM modules, SSD controllers, server motherboards, and any system requiring programmable temperature monitoring and thermal control loop integration.
