SmartDV’s TileLink Verification IP is a comprehensive solution for verifying TileLink, the free and open chip-scale interconnect standard providing coherent memory-mapped access for multiprocessors, accelerators, DMA engines, and peripheral devices in System-on-Chip designs. Fully compliant with TileLink Specification Version 1.9.3 and backward compatible with Version 1.8.1, it supports complete verification of TileLink Master, Slave, Crossbar, Monitor, and Checker components across all three protocol conformance levels including TileLink Uncached Lightweight (TL-UL), TileLink Uncached Heavyweight (TL-UH), and TileLink Cached (TL-C), cache-coherent shared memory, out-of-order completion, and burst fragmentation.
SmartDV’s TileLink VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With fine-grain response control per address or operation, programmable wait states and delay insertion, crossbar delay replication, configurable signal widths, comprehensive error injection, built-in functional coverage, and a complete test suite, SmartDV’s TileLink VIP enables verification teams to thoroughly validate TileLink interconnect designs for RISC-V based SoCs, multi-core processor complexes, domain-specific accelerators, and any system requiring coherent, deadlock-free, scalable on-chip interconnect.
