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SWP VIP

Simulation
Key Features Compliance and Compatibility Request a Datasheet
Overview

SmartDV’s SWP Verification IP is a comprehensive solution for verifying the Single Wire Protocol, the ETSI bit-oriented, point-to-point communication interface between a UICC and a Contactless Frontend enabling NFC card emulation independent of terminal power state. Fully compliant with ETSI TS 102 613 V16.0.0 and ETSI TS 102 221, it supports complete verification of SWP CLF and UICC functionality across the physical layer and data link layer, including the Medium Access Control (MAC) sublayer and Logical Link Control (LLC) sublayer, contact activation and deactivation, and all three defined LLC types including ACT LLC, SHDLC LLC, and CLT LLC.

SmartDV’s SWP VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With all SHDLC frame types, configurable timing functions, CRC-16 CCITT calculation, comprehensive protocol checking, built-in functional coverage, and a complete test suite, SmartDV’s SWP VIP enables verification teams to thoroughly validate SWP interface designs for NFC-enabled mobile devices, secure element controllers, contactless payment systems, and any platform requiring UICC-to-CLF communication for card emulation services.

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SWP VIP
Key Features
  • Full SWP CLF and UICC Support – Provides complete SWP CLF (master) and UICC (slave) component verification across contact activation and deactivation, the physical layer responsible for electrical signaling and connection establishment, and the data link layer split into MAC and LLC sublayers for frame management and error control.
  • LLC Type Coverage – Supports all three defined Logical Link Control types including ACT LLC used during interface activation, SHDLC LLC for the generic link control used during most contactless transactions, and CLT LLC for proprietary protocol handling, covering all defined mandatory and optional LLC behaviors for both CLF and UICC.
  • SHDLC Frame Type Coverage – Supports all SHDLC LLC frame types including I-Frames for information transfer, S-Frames for supervisory functions, and U-Frames for unnumbered control functions, covering complete frame-level protocol behavior for the generic SWP link control layer.
  • Configurable Timing and Data Integrity – Supports configurable timing functions including Acknowledge time, Guarding/Transmit time, and Connection time, along with CRC calculation using the standard CRC-16 CCITT polynomial for complete SWP frame integrity verification.
  • Comprehensive Protocol Checking – Provides continuous monitoring of SWP bus behavior covering all defined transactions, warnings, timing, and protocol violations across full power and low power modes, with complete frame validation per ETSI TS 102 613.
  • Complete Verification Infrastructure – Provides a full test suite covering all SWP specification features, built-in functional coverage analysis, constraints randomization, status counters for bus events, and callbacks in transmitter, receiver, and monitor for user-defined data processing and protocol and timing violation notification.
Compliance and Compatibility
  • Fully compliant with ETSI TS 102 613 V16.0.0; backward compatible with earlier ETSI TS 102 613 versions
  • Compliant with ETSI TS 102 221 (UICC physical and logical characteristics)
  • Supports ACT, SHDLC, and CLT Logical Link Control types
  • Supports CRC-16 CCITT (X16+X12+X5+1) frame error detection
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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