SRAM VIP

Simulation

Key Features Compliance and Compatibility Request a Datasheet

Overview

SmartDV’s SRAM Verification IP is a comprehensive solution for verifying asynchronous Static RAM memory interfaces from all leading vendors, providing accurate SRAM device models for SoC and FPGA designs requiring embedded memory simulation. Compliant with industry-standard asynchronous SRAM device specifications including Cypress/Infineon CY7C199, CY62256, CY62162G/CY62162GE, CY7C1062G/CY7C1062GE, and CY7C1049DV33 across Cypress, Windbond, Motorola, and Cobham parts, it supports complete verification of SRAM read and write cycle operations, complete static memory operation without clock and timing strobe, equal address and chip enable access times, automatic power-down when deselected, and embedded error-correcting code for single-bit error correction.

SmartDV’s SRAM VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With full-timing and behavioral versions in one model, all timing delay ranges including minimum, typical, and maximum, comprehensive protocol checking, built-in functional coverage, and a complete test suite, SmartDV’s SRAM VIP enables verification teams to thoroughly validate SRAM interface designs for embedded processors, FPGAs, cache memory, automotive ECUs, aerospace and radiation-tolerant applications, and any system requiring fast, simple, clockless static memory access.

Request Data Sheet

Key Features

Full SRAM Device Model Support – Provides complete asynchronous SRAM device model verification compliant with 100% of standard SRAM protocol, supporting all SRAM commands per specification, including widely used Cypress/Infineon device models CY7C199, CY7C1049DV33, CY62256, CY62162G/CY62162GE, and CY7C1062G/CY7C1062GE.
Read and Write Cycle Coverage – Supports complete write cycle and read cycle operations, complete static memory operation without clock and timing strobe, and equal address and chip enable access times for verification of fully asynchronous memory access timing behavior.
Device Width Coverage – Supports all defined SRAM device organizations including X4, X8, X16, and X32 widths for comprehensive verification across the full range of common SRAM device configurations and bus interface widths.
Power Management and Error Correction – Supports automated power-down when deselected for low-power standby verification, and embedded error-correcting code for single-bit error correction, supporting verification of radiation-tolerant and high-reliability SRAM device behavior for aerospace and industrial applications.
Comprehensive Protocol Checking – Provides continuous monitoring of SRAM device behavior during simulation, checking Read and Write Command rules and all defined timing violations, with protocol checker fully compliant with SRAM device specifications.
Flexible Timing Model Support – Supports full-timing as well as behavioral versions in a single model, and all timing delay ranges including minimum, typical, and maximum values in a single model for flexible simulation performance and accuracy tradeoffs.
Complete Verification Infrastructure – Provides built-in functional coverage analysis and callbacks for user access to monitor-observed data across all SRAM protocol conditions covering normal operation and timing violation scenarios.

Compliance and Compatibility

Compliant with industry-standard asynchronous SRAM device specifications
Supports Cypress/Infineon CY7C199, CY7C1049DV33, CY62256, CY62162G/CY62162GE, and CY7C1062G/CY7C1062GE device models
Supports Windbond, Motorola, and Cobham SRAM part numbers
Supports X4, X8, X16, and X32 device organizations
Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

Request Datasheet