SmartDV’s SPI Synthesizable Transactor is a fully featured Serial Peripheral Interface bus model purpose-built for hardware emulation and FPGA prototyping environments requiring fast, accurate, and highly configurable SPI Master and Slave behavior during pre-silicon validation of embedded, automotive, IoT, and consumer electronics SoC designs. Compliant with SPI Block Guide v4.01 and compatible with NAND and NOR flash devices from all major vendors, it delivers complete Master and Slave functionality supporting Single, Dual, Quad, and Octal data widths in both SDR and DDR modes with up to 16 slave devices under master control, giving validation teams a drop-in synthesizable SPI transactor ready for rapid integration into emulation and prototyping flows.
Designed for the speed and visibility demands of emulation and FPGA prototyping rather than ASIC tape-out, the transactor emphasizes fast bring-up, fine-grained controllability, and on-the-fly protocol checking over area or power optimization. It supports 3-wire and 4-wire operation, full and half duplex modes, bi-directional mode, TI and National Semiconductor Microwire compatibility, programmable clock polarity and phase, LSB and MSB data ordering, Programmed IO, Boot, and XIP data transfer modes, individually controllable chip-select, write protect and hold signal pins, mode fault error detection, and configurable FIFO architecture, enabling validation teams to exercise corner-case SPI behavior that is difficult to reach with production RTL alone.
Built for fast compile times and efficient resource utilization on hardware emulation and FPGA prototyping platforms, the transactor is fully synthesizable and platform-independent, deployable on any hardware emulation or FPGA prototyping platform. Its comprehensive error injection capabilities, software and hardware reset support, threshold-based interrupt generation, and testbench notification of significant events, warnings, timing, and protocol violations enable rapid deployment for early software bring-up and SPI system-level validation regardless of the underlying emulation platform.
