SmartDV’s S/PDIF Verification IP is a comprehensive solution for verifying the Sony/Philips Digital Interface, the ubiquitous digital audio serial interface used to transport linear and non-linear PCM encoded audio between consumer electronics, professional audio equipment, and embedded audio subsystems. Fully compliant with IEC 60958 for digital audio interface and IEC 61937 for non-linear PCM encoded audio bitstream transport, and supporting SMPTE 337M for non-linear PCM and AES/EBU and AES3 for professional linear PCM audio, it supports complete verification of S/PDIF transmitter and receiver components across all defined sampling rates from 22.05 kHz through 1536 kHz, 32 audio channels, biphase-mark code encoding, clock recovery, start bit correction, and all defined error conditions.
SmartDV’s S/PDIF VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With configurable baud rate control, comprehensive error injection across all S/PDIF error types, on-the-fly protocol and data checking, built-in functional coverage, and a complete test suite, SmartDV’s S/PDIF VIP enables verification teams to thoroughly validate S/PDIF interface designs for consumer AV receivers, Blu-ray players, soundbars, gaming consoles, professional audio interfaces, studio equipment, and embedded audio SoC applications.
