SmartDV’s SpaceWire Verification IP is a comprehensive solution for verifying SpaceWire, the ECSS high-speed data-handling interconnect providing a unified infrastructure for connecting sensors, processing elements, mass-memory units, and downlink telemetry subsystems on board spacecraft. Fully compliant with ECSS-E-ST-50-12C Rev.1 (15 May 2019), it supports complete verification of SpaceWire Host and Node components across speeds between 2 Mb/s and 400 Mb/s, full-duplex point-to-point serial data communication links, Data-Strobe (DS) encoding, link initialization and flow control, Time-Code support, and four arbitration schemes including priority-based, round-robin, random, and first-come-first-served.
SmartDV’s SpaceWire VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With link error recovery, exchange of silence error recovery procedure, on-the-fly protocol and data checking, complete Remote Memory Access Protocol handling per ECSS-E-ST-50-52C, comprehensive error injection and detection, built-in functional coverage, and a complete test suite, SmartDV’s SpaceWire VIP enables verification teams to thoroughly validate SpaceWire interface designs for satellite payload data handling, onboard processing systems, mass-memory units, and spacecraft data-handling infrastructure requiring standardized, reusable, mission-independent interconnect.
