SmartDV’s SGPIO Verification IP is a comprehensive solution for verifying the Serial General Purpose Input Output bus, the SFF Committee standard for communicating drive slot status and enclosure management information between a host bus adapter and a storage backplane in SAS, SATA, and PCI Express storage systems. Fully compliant with SFF-8485 Specification for Serial GPIO Bus Revision 0.7, it supports complete verification of SGPIO Initiator and Target components across operating frequencies from 33 Hz to 100 kHz, support for up to 256 hard disk drives, both Normal and General-Purpose initiator operating modes, configurable SCLK high and low time, dual blink generators for output pattern control, and the complete set of GPIO configuration, receive, general-purpose receive, transmit, and general-purpose transmit registers.
SmartDV’s SGPIO VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With status counters for bus events, comprehensive protocol checking, built-in functional coverage, and a complete test suite, SmartDV’s SGPIO VIP enables verification teams to thoroughly validate SGPIO interface designs for storage host bus adapters, RAID controllers, storage backplanes, and enclosure management systems requiring standardized drive activity, locate, and fail LED indication across SAS and SATA storage arrays.
