SmartDV’s SDRAM Verification IP is a comprehensive solution for verifying Synchronous Dynamic Random Access Memory controller interfaces, providing accurate SDR SDRAM device models for SoC and FPGA designs requiring embedded memory simulation. Compliant with the JEDEC JESD21-C Section 3.11 SDR SDRAM standard and the Hynix HY57V56820FT-H 512Mb SDR SDRAM device specification, it supports complete verification of SDR SDRAM controller and device interactions across programmable burst lengths from 1 to full page, all refresh modes, internal bank management, all mode register programming, auto-precharge including concurrent auto-precharge, power-up, initialization, and power-off sequencing, and all defined timing parameters for speed grades -7E and -75.
SmartDV’s SDRAM VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With bus-accurate timing for minimum, maximum, and typical values, comprehensive protocol checking covering all state-based rules, command rules, and timing violations, continuous bus monitoring, built-in functional coverage, and callbacks for user data access, SmartDV’s SDRAM VIP enables verification teams to thoroughly validate SDR SDRAM controller interface designs for embedded processors, FPGAs, SoCs, DSPs, and any application using synchronous DRAM for main memory or frame buffer storage.
