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Overview

SmartDV’s RoE Verification IP is a comprehensive solution for verifying Radio over Ethernet, the IEEE standard defining encapsulation and mapping of radio protocols for transport over Ethernet frames and IP packets in fronthaul transport networks. Fully compliant with IEEE 1914.3-2023 and backward compatible with IEEE 1914.3-2018, it supports complete verification of RoE TX BFM, RX BFM, and Monitor components across up to 256 RoE mappers and de-mappers, all seven defined RoE subtypes covering structure-agnostic, structure-aware CPRI, control, slow C&M CPRI, native time domain, native frequency domain, and native PRACH data, I/Q data sample mapping, control and management data transfer, and Ethernet speeds from 10G to 400G.

SmartDV’s RoE VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With comprehensive error injection across all Ethernet physical and protocol layers, scrambler error insertion, glitch insertion, pause frame generation and detection, bus-accurate timing, built-in functional coverage, and a complete test suite, SmartDV’s RoE VIP enables verification teams to thoroughly validate Radio over Ethernet fronthaul interface designs for 4G/5G mobile radio fronthaul, Open RAN, distributed antenna systems, and any Ethernet-based packetized fronthaul transport network.

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RoE VIP
Key Features
  • Full RoE Mapper and De-mapper Support – Provides complete RoE TX BFM, RX BFM, and Monitor component verification supporting up to 256 RoE mappers and de-mappers, encapsulation and de-encapsulation functions across all defined locations, encapsulation transport format verification, mapping of each individual I/Q data sample, and control and management data transfer.
  • Comprehensive RoE Subtype Coverage – Supports all seven defined IEEE 1914.3 RoE subtypes including RoE Control subtype for link management, RoE Structure-Agnostic Data subtype for any digitized radio data regardless of format, RoE Structure-Aware CPRI Data subtype for CPRI frame and payload mapping, RoE Slow C&M CPRI subtype for CPRI control and management channel transport, Native RoE Time Domain Data subtype for time-domain I/Q payload, Native RoE Frequency Domain Data subtype for frequency-domain I/Q payload, and RoE Native PRACH Data subtype for Physical Random Access Channel data.
  • Comprehensive Ethernet Speed Coverage – Supports all defined fronthaul Ethernet transport speeds including 10G, 25G, 40G, 50G, 100G, 200G, and 400G for complete fronthaul transport verification across all defined deployment scenarios and radio access network architectures.
  • Comprehensive Error Injection and Detection – Supports insertion of scrambler errors, glitch insertion and detection, and all defined TX and RX error types at each protocol layer including undersize and oversize frames, CRC errors, framing errors, pause frame errors, disparity and auto-negotiation errors, invalid code group insertion, invalid /K/ character insertion, lane skew insertion, invalid AN sequence errors, and missing /K/ characters for packet boundaries.
  • Complete Verification Infrastructure – Provides a full test suite covering all IEEE 1914.3-2023 specification features, built-in functional coverage analysis, bus-accurate timing checks, constraints randomization, status counters for bus events, pause frame generation and detection, and callbacks in TX, RX, and Monitor for user-defined data processing and protocol and timing violation notification.
Compliance and Compatibility
  • Fully compliant with IEEE 1914.3-2023 (Radio over Ethernet Encapsulations and Mappings); backward compatible with IEEE 1914.3-2018
  • Supports up to 256 RoE mappers and de-mappers
  • Supports all seven defined RoE subtypes including structure-agnostic, structure-aware CPRI, and native mode
  • Supports Ethernet transport at 10G, 25G, 40G, 50G, 100G, 200G, and 400G
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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