SmartDV’s RoCE Verification IP is a comprehensive solution for verifying RDMA over Converged Ethernet, the InfiniBand Trade Association standard that enables Remote Direct Memory Access over Ethernet networks for AI training, high-performance computing, storage clustering, and low-latency data center applications. Fully compliant with RoCEv1 as an Ethernet link layer protocol and RoCEv2 over UDP/IPv4 and UDP/IPv6, it supports complete verification of RoCE TX BFM, RX BFM, and Monitor components across all four InfiniBand transport services, all defined transport operations, Base Transport Header and Extended Transport Header formats, queue pair management, ACK/NAK transmission, packet fragmentation, Priority Flow Control, and Ethernet speeds from 10G to 400G.
SmartDV’s RoCE VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive error injection across all protocol layers, glitch insertion, scrambler error insertion, pause frame generation and detection, bus-accurate timing, built-in functional coverage, and a complete test suite, SmartDV’s RoCE VIP enables verification teams to thoroughly validate RoCE network interface designs for AI accelerator interconnects, NVMe-oF storage fabric, high-frequency trading, hyperscale data center fabric, and any RDMA-capable Ethernet NIC or SmartNIC application.
