Contact Us
Overview

SmartDV’s PSI5 Verification IP is a comprehensive solution for verifying the Peripheral Sensor Interface 5, the open standard two-wire current interface for connecting peripheral sensors to electronic control units in automotive electronics. Fully compliant with PSI5 Specification Version 2.3, it supports complete verification of PSI5 ECU and Sensor components across the Manchester-coded current-modulated digital interface at 125 kbps and optional 189 kbps, asynchronous and synchronous bus modes, bidirectional communication, variable data word lengths from 10 to 28 bits, and all three defined error detection methods including single-bit parity, 3-bit CRC, and 6-bit CRC.

SmartDV’s PSI5 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With high EMC robustness and low emission characteristics modeled in the interface, all defined bus mode configurations, complete bidirectional communication coverage, built-in functional coverage, and a complete test suite, SmartDV’s PSI5 VIP enables verification teams to thoroughly validate PSI5 sensor interface designs for automotive airbag systems, chassis safety, powertrain sensors, ADAS sensor fusion ECUs, and all peripheral sensor applications requiring reliable current-loop automotive connectivity.

Request Data Sheet
Key Features
  • Full PSI5 ECU and Sensor SupportProvides complete PSI5 ECU and Sensor component verification across the two-wire current-modulated Manchester-coded interface, supporting data transmission rates of 125 kbps and optional 189 kbps, variable data word lengths from 10 to 28 bits with 1-bit granularity, bidirectional communication, and all defined point-to-point and bus topologies.
  • Bus Mode and Synchronization Coverage – Supports asynchronous and synchronous operating modes and all defined PSI5 bus mode configurations, covering both sensor-to-ECU uplink data frames and ECU-to-sensor downlink command transmission across all defined frame structures and time slot configurations.
  • Manchester Encoding and Physical Layer – Supports Manchester-coded digital data transmission with high EMC robustness and low emission characteristics, current-modulated interface operation over two-wire twisted pair, and all defined PSI5 physical layer timing parameters for complete sensor-to-ECU signal integrity verification.
  • Error Detection Method CoverageSupports all three defined PSI5 error detection methods including single-bit parity for basic transmission error detection, 3-bit CRC for enhanced error detection coverage, and 6-bit CRC for maximum data integrity protection across all defined data word lengths and bus configurations.
  • Complete Verification Infrastructure – Provides built-in functional coverage analysis covering all PSI5 v2.3 specification features, status counters for bus events, and callbacks in ECU and Sensor for user-defined event handling and protocol and timing violation notification.
Compliance and Compatibility
  • Fully compliant with PSI5 Specification Version 2.3; backward compatible with PSI5 v2.0, v1.3, and earlier versions
  • Supports 125 kbps and optional 189 kbps data transmission rates
  • Supports variable data word lengths from 10 to 28 bits with 1-bit granularity
  • Supports single-bit parity, 3-bit CRC, and 6-bit CRC error detection methods
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

Request Datasheet