SmartDV’s PCI Verification IP is a comprehensive solution for verifying the Peripheral Component Interconnect local bus, the foundational parallel shared bus standard for expansion card and peripheral connectivity in embedded, industrial, and legacy computer system designs. Fully compliant with PCI Local Bus Specification Revision 3.0 and Revision 2.3, it supports complete verification of PCI Master, Slave, Arbiter, and Monitor components across 32-bit and 64-bit address and data configurations, all defined PCI transaction types, all DEVSEL timing modes, data bursting for back-to-back access, multi-master and multi-slave configurations, INTA through INTD interrupt signaling, configurable error injection, and configurable delay insertion in both master and slave.
SmartDV’s PCI VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With a 100% PCI specification-compliant arbiter, comprehensive error and delay injection, multi-master and multi-slave support for complex PCI subsystem verification, built-in functional coverage, and a complete test suite, SmartDV’s PCI VIP enables verification teams to thoroughly validate PCI interface designs for industrial controllers, embedded compute platforms, legacy I/O bridge designs, FPGA-based PCI controllers, and PCIe-to-PCI bridge verification.
