SmartDV’s Parallel NOR Flash Verification IP is a comprehensive solution for verifying parallel NOR flash memory interfaces, the directly addressable, randomly readable non-volatile storage technology used in embedded control, automotive, industrial, and FPGA configuration applications requiring fast code execute-in-place and high-reliability data storage. Compliant with the JEDEC Common Flash Interface (CFI) specification JESD68-01 and industry-standard parallel NOR flash device specifications, it supports complete verification of parallel NOR flash host controller and device components across x8 and x16 data bus configurations, densities from 128 Mb to 2 Gb, asynchronous random and page read, buffer program, word and byte program, block and chip erase, program and erase suspend and resume, blank check, CRC, extended memory blocks, and all defined security and write protection modes.
SmartDV’s Parallel NOR Flash VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With unlock bypass, non-volatile, volatile, and password-based write protection, continuous monitoring of all protocol and timing violations, built-in functional coverage, and a complete test suite, SmartDV’s Parallel NOR Flash VIP enables verification teams to thoroughly validate parallel NOR flash interface designs for automotive ECUs, industrial controllers, medical devices, FPGA configuration memory, and any embedded application requiring reliable parallel NOR flash storage.
