SmartDV’s O-RAN Verification IP is a comprehensive solution for verifying the O-RAN Alliance Open Fronthaul interface, the Lower Layer Split Option 7.2x interface connecting O-RAN Distributed Units and Radio Units in open, multi-vendor 5G and beyond radio access networks. Fully compliant with O-RAN WG4 CUS-Plane Specification v18.00 (June 2025) and backward compatible with earlier versions including v6.0, it supports complete verification of O-RU and O-DU TX and RX functionality across Ethernet and IP/UDP encapsulation, eCPRI and RoE transport headers, all four defined planes including C-Plane, U-Plane, S-Plane, and M-Plane, CTI Message Protocol, all defined eCPRI message types, U-law and Block Floating Point compression, and Ethernet speeds from 10G to 400G.
SmartDV’s O-RAN VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive application layer and radio transport layer fragmentation, scrambler error injection, glitch injection, comprehensive error injection and detection at all protocol layers, bus-accurate timing, built-in functional coverage, and a complete test suite, SmartDV’s O-RAN VIP enables verification teams to thoroughly validate open fronthaul interface designs for 5G O-RU silicon, O-DU ASICs and FPGAs, fronthaul switches, and multi-vendor Open RAN deployments.