Contact Us
Overview

SmartDV’s O-RAN Verification IP is a comprehensive solution for verifying the O-RAN Alliance Open Fronthaul interface, the Lower Layer Split Option 7.2x interface connecting O-RAN Distributed Units and Radio Units in open, multi-vendor 5G and beyond radio access networks. Fully compliant with O-RAN WG4 CUS-Plane Specification v18.00 (June 2025) and backward compatible with earlier versions including v6.0, it supports complete verification of O-RU and O-DU TX and RX functionality across Ethernet and IP/UDP encapsulation, eCPRI and RoE transport headers, all four defined planes including C-Plane, U-Plane, S-Plane, and M-Plane, CTI Message Protocol, all defined eCPRI message types, U-law and Block Floating Point compression, and Ethernet speeds from 10G to 400G.

SmartDV’s O-RAN VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With comprehensive application layer and radio transport layer fragmentation, scrambler error injection, glitch injection, comprehensive error injection and detection at all protocol layers, bus-accurate timing, built-in functional coverage, and a complete test suite, SmartDV’s O-RAN VIP enables verification teams to thoroughly validate open fronthaul interface designs for 5G O-RU silicon, O-DU ASICs and FPGAs, fronthaul switches, and multi-vendor Open RAN deployments.

Request Data Sheet
O-RAN VIP
Key Features
  • Full O-RU and O-DU TX and RX Support – Provides complete O-RAN Radio Unit and Distributed Unit TX and RX functionality verification across Ethernet encapsulation and IP/UDP encapsulation transport options, eCPRI and IEEE 1914.3 RoE transport headers, and application layer and radio transport layer fragmentation for large data transfers.
  • Comprehensive Plane CoverageSupports all four defined O-RAN fronthaul planes including C-Plane for scheduling and beam management control, U-Plane for IQ sample data transport, S-Plane for fronthaul synchronization using PTP and SyncE across LLS-C1 through LLS-C4 synchronization configurations, and M-Plane for O-RU management and configuration, along with CTI Message Protocol support.
  • eCPRI Message Type CoverageSupports all defined eCPRI message types including IQ Data messages for U-Plane sample transport, Real-Time Control Data messages for C-Plane scheduling information, and Delay Measurement messages for fronthaul latency characterization and timing alignment.
  • Compression Method SupportSupports U-law compression for logarithmic IQ sample quantization and Block Floating Point compression for efficient IQ sample packing, covering all defined compression header formats and compression parameters for both downlink and uplink data paths.
  • Comprehensive Ethernet Speed Coverage – Supports all defined O-RAN fronthaul Ethernet speeds including 10G, 25G, 40G, 50G, 100G, 200G, and 400G for complete fronthaul transport verification across all defined deployment scenarios.
  • Comprehensive Error Injection and Detection – Supports insertion of scrambler errors, glitch injection and detection, and all defined TX and RX error types at each protocol layer including undersize and oversize frames, CRC errors, framing errors, pause frame errors, disparity and auto-negotiation errors, invalid code group insertion, invalid /K/ character insertion, lane skew insertion, invalid AN sequence errors, and missing /K/ characters for packet boundaries.
  • Complete Verification Infrastructure – Provides a full test suite covering all O-RAN WG4 CUS-Plane specification features, built-in functional coverage analysis, bus-accurate timing checks, status counters for bus events, and callbacks in TX, RX, and Monitor for user-defined data processing and protocol and timing violation notification.
Compliance and Compatibility
  • Fully compliant with O-RAN WG4 CUS-Plane Specification v18.00 (June 2025); backward compatible with earlier versions including v6.0
  • Supports Ethernet encapsulation and IP/UDP encapsulation transport options
  • Supports eCPRI and IEEE 1914.3 RoE transport headers
  • Supports 10G, 25G, 40G, 50G, 100G, 200G, and 400G Ethernet fronthaul speeds
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

Request Datasheet