Open NAND Flash Interface (ONFI) VIP

Simulation

Key Features Compliance and Compatibility Request a Datasheet

Overview

SmartDV’s ONFI Verification IP is a comprehensive solution for verifying the Open NAND Flash Interface, the industry-standard protocol enabling multi-vendor interoperability between NAND flash memory devices and host controllers in SSDs, mobile devices, and embedded storage applications. Fully compliant with ONFI 5.2 (October 2024) and backward compatible with ONFI 5.0, 4.1, 4.0, 3.0, and 2.3, it supports complete verification of ONFI host controller and NAND flash device components across asynchronous and source-synchronous data interfaces, all five defined data interface types from SDR through NV-LPDDR4, 8-bit and 16-bit bus width operation, all mandatory and optional commands, multi-LUN, interleaved and multi-plane operations, dual data bus, data bus inversion, all training modes, vendor-specific commands, and Block Abstracted NAND commands.

SmartDV’s ONFI VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With comprehensive training mode coverage including implicit DCC, read DQ, write TX DQ, and write RX DQ training, partial page and copy-back programming, small data move, volume select, clock stop, configurable timing modes for all data interfaces, on-the-fly protocol and data checking, built-in functional coverage, and a complete test suite, SmartDV’s ONFI VIP enables verification teams to thoroughly validate NAND flash interface designs for enterprise SSDs, client storage controllers, mobile storage, embedded NAND controllers, and any application requiring high-bandwidth multi-vendor NAND flash interoperability.

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Open NAND Flash Interface (ONFI) VIP

Key Features

Full ONFI Host Controller and Device Support – Provides complete ONFI host controller and NAND flash device component verification with support for asynchronous and source-synchronous data interfaces, 8-bit and 16-bit bus width operations, all mandatory and optional commands, dual data bus, multiple LUN operation, and a rich set of configuration parameters for fine-grain protocol control.
Comprehensive Data Interface Coverage – Supports all five defined ONFI data interfaces including SDR asynchronous, DDR synchronous, NV-DDR2, NV-DDR3 at speeds up to 1600 MT/s, and NV-LPDDR4 at speeds up to 3600 MT/s as defined in ONFI 5.1/5.2, with configurable timing modes for each interface type and source synchronous clock stop feature.
Training Mode Coverage – Supports Implicit DCC Training commands, Read DQ Training commands, Write TX DQ Training Pattern commands, Write TX DQ Training Readback commands, and Write RX DQ Training commands for complete high-speed interface training and calibration verification across all NV-DDR3 and NV-LPDDR4 operating modes.
Advanced Command and Operation Coverage – Supports Read ID, Synchronous Reset, Reset LUN, Get Features, Set Features, Volume Select, Interleaved and Multi-plane commands, Small Data Move for both Program and Copy-back operations, partial page programming, copy-back programming, vendor-specific commands, and Block Abstracted NAND commands.
Data Integrity and Advanced Features – Supports Data Bus Inversion, dual data bus operation, Separate Command Address Protocol as introduced in ONFI 5.2, configurable timing modes for all data interfaces, and on-the-fly protocol and data checking across all ONFI operating configurations.
Comprehensive Error Detection and Reporting – Detects and reports all defined ONFI error types including page address errors, CRC errors, command not supported errors, illegal command errors, synchronous reset errors, Read ID errors, Reset LUN errors, read cache errors, read UID errors, LUN address change errors, copy-back program errors, change row address errors, read status enhanced errors, and interleave page address errors.
Complete Verification Infrastructure – Provides a full test suite covering all ONFI 5.2 specification features, built-in functional coverage analysis, constraints randomization, status counters for bus events, and callbacks in host, slave, and monitor for user-defined data processing and protocol and timing violation notification.

Compliance and Compatibility

Fully compliant with ONFI 5.2 (October 2024); backward compatible with ONFI 5.0, 4.1, 4.0, 3.0, and 2.3
Supports SDR, DDR, NV-DDR2, NV-DDR3, and NV-LPDDR4 data interfaces up to 3600 MT/s
Supports 8-bit and 16-bit bus width with dual data bus and Data Bus Inversion
Supports Block Abstracted NAND and Separate Command Address Protocol per ONFI 5.2
Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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