SmartDV’s OCP Verification IP is a comprehensive solution for verifying the Open Core Protocol, the openly licensed, bus-independent, core-centric on-chip subsystem communication protocol enabling configurable, scalable IP core integration across heterogeneous SoC designs. Fully compliant with Open Core Protocol Specification 3.0 as maintained by Accellera Systems Initiative, it supports complete verification of OCP Master, Slave, Monitor, and Checker components across all protocol transfer and command types, all signal widths, all burst models and response types, SRMD and MRMD bursts, pipelined and non-blocking transfers, multi-threading, tagging, request interleaving, out-of-order processing, 2-dimensional block burst address sequences, coherence extensions, and the full range of OCP configuration parameters.
SmartDV’s OCP VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With Master/Slave connect-disconnect, asynchronous and synchronous reset, EnableClk mechanism, on-the-fly reset control, ThreadBusy behavior, all sideband signals, fine-grain slave response control, programmable timeout insertion, FIFO memory support, on-the-fly protocol and data checking, built-in functional coverage, and a complete test suite, SmartDV’s OCP VIP enables verification teams to thoroughly validate OCP interface designs for SoC IP integration, embedded processors, memory controllers, peripheral subsystems, and legacy OCP-based IP reuse applications.
