SmartDV’s NVMe Verification IP is a comprehensive solution for verifying the Non-Volatile Memory Express host controller interface, the industry-standard high-performance storage protocol connecting SSDs and other non-volatile memory devices across PCIe and fabric transports. Fully compliant with the NVMe 2.3 Base Specification (August 2025) and backward compatible through NVMe 1.4, it supports complete verification of NVMe host and device components across all Admin and I/O commands, submission and completion queue management, namespace subsystem, controller memory buffer, PRP and SGL memory description, boot partitions, metadata, doorbell buffer, reservation and directive features, end-to-end data protection, and NVMe over PCIe transport with full PCIe protocol stack coverage through PCIe 6.0 including PAM4, Flit mode, Forward Error Correction, L0p state, and PIPE 5.2.1.
SmartDV’s NVMe VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive automated error injection at all protocol layers, UNH-IOL test suite support, configurable VC queuing, TC to VC mapping, SERDES model with digital clock recovery, spread spectrum clocking, polarity inversion, lane skew, built-in functional coverage, and a complete test suite, SmartDV’s NVMe VIP enables verification teams to thoroughly validate NVMe storage interface designs for enterprise SSDs, data center AI storage, hyperscale cloud infrastructure, client NVMe SSDs, and embedded storage applications.
