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Overview

SmartDV’s MIL-STD-1773 Verification IP is a comprehensive solution for verifying the fiber optic mechanization of the aircraft internal time division command/response multiplex data bus, providing the same MIL-STD-1553B protocol over fiber optic transmission for enhanced electromagnetic immunity, radiation tolerance, and extended range in military aircraft, spacecraft, and defense systems. Fully compliant with MIL-STD-1773 and its Notice 1 administrative update, it supports complete verification of Bus Controller, Remote Terminal, and Bus Monitor components across single, dual, and quad channel dual-redundant bus configurations, all five message format types, all four defined optical encoding schemes, and up to 31 remote terminals, with comprehensive error injection and detection across all defined MIL-STD-1773 error types.

SmartDV’s MIL-STD-1773 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With NRZ, Manchester II bi-phase, PTMBC, and EMBC-BSF optical encoding support, configurable word and data widths, glitch injection, on-the-fly protocol and data checking, bus-accurate timing, programmable FIFO depth, built-in functional coverage, and a complete test suite, SmartDV’s MIL-STD-1773 VIP enables verification teams to thoroughly validate fiber optic avionics data bus interface designs for military aircraft, spacecraft, satellites, missiles, and radiation-hardened defense electronics.

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MIL-STD-1773 VIP
Key Features
  • Full BC, RT, and BM SupportProvides complete Bus Controller, Remote Terminal, and Bus Monitor component verification with support for single, dual, and quad channel dual-redundant bus configurations, single and multi-bus control, up to 31 remote terminals, configurable word length defaulting to 20 bits, configurable data width defaulting to 16 bits, configurable message length per transfer, and programmable FIFO depth.
  • Comprehensive Optical Encoding Coverage – Supports all four MIL-STD-1773 defined encoding and decoding types including NRZ coding, Manchester II bi-phase coding, Partial Trilevel Manchester II bi-phase coding for rejection of impulsive interference in optical bus implementations, and Extended Manchester II bi-phase coding with beginning-stopping flags for enhanced synchronization in high-noise environments.
  • Message Format Coverage – Supports all five MIL-STD-1773 message format types including Controller to Terminal, Terminal to Controller, Terminal to Terminal, Broadcast, and System Control transfers, covering all defined optical word format types including command words, status words, and data words.
  • Comprehensive Error Injection and Detection – Supports injection and detection of all defined MIL-STD-1773 error types including command word sync errors, data word sync errors, status word sync errors, command/data/status word parity errors, NRZ and Manchester encoding errors, bi-phase encoding errors, low and high bi-phase encoding errors, oversize and undersize data word errors, extra and less data word errors, various illegal command errors, inter-message gap errors, terminal response timeout errors, and glitch injection and detection.
  • Complete Verification Infrastructure – Provides on-the-fly protocol and data checking, bus-accurate timing and timing checks, constraints randomization, built-in functional coverage analysis, status counters for bus events, and callbacks in Bus Controller and Remote Terminal for user-defined event handling and protocol and timing violation notification.
Compliance and Compatibility
  • Fully compliant with MIL-STD-1773 (May 1988) and Notice 1 (May 2017)
  • Fiber optic mechanization of MIL-STD-1553B protocol with identical command/response operation
  • Supports NRZ, Manchester II bi-phase, PTMBC, and EMBC-BSF optical encoding schemes
  • Supports single, dual, and quad channel dual-redundant bus configurations with up to 31 remote terminals
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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