LVDS VIP

Simulation

Benefits Compliance and Compatibility Request a Datasheet

Overview

SmartDV’s LVDS Verification IP is a comprehensive solution for verifying the Low Voltage Differential Signal IQ data interface of the Microchip AT86RF215 dual-band sub-1GHz and 2.4GHz transceiver, a widely deployed RF front-end IC used in IEEE 802.15.4, smart metering, industrial IoT, and wireless sensor network applications. Compliant with the Microchip AT86RF215 datasheet specification (formerly Atmel-42415-WIRELESS-AT86RF215), it supports complete verification of BBIC and RFIC components across the 13-bit LVDS IQ data interface for both transmit and receive signal paths, covering half-duplex DDR data transfer, TXD, RXD09, and RXD24 IQ data streams, 2-bit SYNC signals, 14-bit I and Q data, and the SPI transceiver control interface with single and burst transfer modes.

SmartDV’s LVDS VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With comprehensive error injection and detection across all defined AT86RF215 LVDS error types, SPI master and slave mode support, baud rate selection, built-in functional coverage, and a complete test suite, SmartDV’s AT86RF215 LVDS VIP enables verification teams to thoroughly validate AT86RF215-based RF front-end interface designs for IEEE 802.15.4g, smart metering, home energy gateways, industrial IoT, and wireless sensor network SoC applications.

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LVDS VIP

Benefits

Full BBIC and RFIC Support – Provides complete BBIC and RFIC component verification across the AT86RF215 13-bit LVDS IQ data interface, supporting half-duplex DDR data transfer at 64 MHz LVDS clock frequency, TXD transmit path, RXD09 sub-1GHz receive path, and RXD24 2.4GHz receive path signal streams.
IQ Data Path Transaction Coverage – Supports all AT86RF215 IQ data path transactions including 2-bit I SYNC and Q SYNC synchronization data, 14-bit I data and Q data streams, DDR edge-aligned transmit and center-aligned receive data timing, and LVDS clock skew configuration for external baseband processor interface timing alignment.
SPI Control Interface Coverage – Supports all AT86RF215 SPI transceiver control interface transactions including 2-bit command plus 14-bit address and 8-bit data control field format, master and slave mode operation, baud rate selection, single transfer mode, and burst transfer mode for complete device register access verification.
Comprehensive Error Injection and Detection – Supports injection and detection of all defined AT86RF215 LVDS error types including I SYNC errors, Q SYNC errors, invalid zero word errors, illegal write data errors, and read-only address errors for thorough protocol violation verification.
Complete Verification Infrastructure – Provides a full test suite covering all AT86RF215 LVDS interface specification features, built-in functional coverage analysis, status counters for bus events, and callbacks in BBIC and RFIC for user-defined event handling and protocol and timing violation notification.

Compliance and Compatibility

Compliant with Microchip AT86RF215 datasheet specification (Atmel-42415-WIRELESS-AT86RF215) for LVDS IQ data interface and SPI transceiver control interface
Based on IEEE 1596.3-1996 LVDS signaling standard
Supports AT86RF215, AT86RF215IQ, and AT86RF215M device variants
Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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