SmartDV’s LPDDR3 Verification IP is a comprehensive solution for verifying Low Power Double Data Rate 3 memory interfaces, the high-bandwidth, power-efficient DRAM standard widely deployed in smartphones, tablets, ultra-thin notebooks, and mobile computing devices. Fully compliant with JEDEC JESD209-3C and backward compatible with JESD209-3B and JESD209-3, it supports complete verification of LPDDR3 device components across x16 and x32 device configurations with densities up to 32 GB, covering all defined commands, mode register programming, write leveling, ZQ calibration, CA training, DQ calibration, ODT, power down, deep power down, and all timing delay ranges in both full-timing and behavioral models.
SmartDV’s LPDDR3 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With bus-accurate timing for minimum, typical, and maximum delay ranges in a single model, comprehensive power management feature coverage, write data mask and data strobe verification, input clock stop and frequency change, built-in functional coverage, and a complete test suite, SmartDV’s LPDDR3 VIP enables verification teams to thoroughly validate LPDDR3 memory interface designs for mobile SoCs, application processors, automotive infotainment, and power-sensitive embedded computing applications.
