SmartDV’s JESD403 Verification IP is a comprehensive solution for verifying the JEDEC Module Sideband Bus (SidebandBus), the system management control bus standard for DDR5 memory modules and next-generation memory solutions. Fully compliant with JESD403-1C.01-2024 and developed in coordination with the MIPI Alliance as both a subset and superset of the MIPI I3C Basic serial bus standard, it supports complete verification of JESD403 Host Controller and Device components across the two-wire serial interface at up to 12.5 MHz, covering dynamic address assignment with legacy I2C static addressing, in-band interrupts, all Common Command Codes, timed reset, write and read formats, PEC, and all defined error conditions for both host and device sides.
SmartDV’s JESD403 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With 7-bit configurable slave addressing, master SCL clock stalling, slave response field control including NACK, data, and slave busy responses, slave error types S1 and S2, comprehensive error injection, built-in functional coverage, and a complete test suite, SmartDV’s JESD403 VIP enables verification teams to thoroughly validate SidebandBus interface designs for DDR5 RDIMM, LRDIMM, and SODIMM systems, power management ICs, temperature sensors, SPD hubs, and next-generation memory module management applications.