SmartDV’s JESD207 Verification IP is a comprehensive solution for verifying the Radio Front End — Baseband Digital Parallel (RBDP) interface, the JEDEC standard defining the data path and control plane interface between Radio Front-End Integrated Circuits and Baseband Integrated Circuits in wireless networking and mobile communication designs. Fully compliant with JEDEC JESD207, it supports complete verification of BBIC and RFIC components across half-duplex DDR source-synchronous data transfers, multiple parallel sample streams, all defined data path transaction types, and all control plane transaction formats including 3-wire and 4-wire read and write operations.
SmartDV’s JESD207 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive data path coverage including 10-bit and 12-bit sample widths, 2-way and 4-way interleave, 1T1R, 1T2R, and 2T2R antenna system support, extended data transactions, error injection and detection, constraints randomization, built-in functional coverage, and a complete test suite, SmartDV’s JESD207 VIP enables verification teams to thoroughly validate RFIC-BBIC interface designs for wireless LAN, mobile devices, software-defined radio, and embedded wireless networking applications.
