SmartDV’s Interlaken Verification IP is a comprehensive solution for verifying the Interlaken scalable chip-to-chip packet transfer protocol used in high-bandwidth networking, data center, and telecommunications equipment. Fully compliant with Interlaken Protocol Specification v1.2, Interlaken Look-Aside Protocol v1.1, Interlaken Retransmission Extension v1.2, Interlaken Reed-Solomon FEC Extension v1.1, Interlaken Interoperability Recommendations v1.11, and Interlaken Dual Calendar Extension v1.0, it supports complete verification of Interlaken TX BFM, RX BFM, and Monitor components across configurable 1 to 64 lane implementations, multi-channel operation, 64B/67B encoding, and the full suite of Interlaken protocol extensions.
SmartDV’s Interlaken VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With configurable burst and meta-frame parameters, scheduling calendar logic, per-lane CRC-32 diagnostics, comprehensive error injection across all Interlaken error types, test pattern generation and checking, 67-bit bus and serial lane interface options, configurable SerDes interface widths, on-the-fly protocol checking, built-in functional coverage, and a complete test suite, SmartDV’s Interlaken VIP enables verification teams to thoroughly validate Interlaken interface designs for networking switches, routers, data center fabric interconnects, NPUs, and high-performance computing applications.
