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Overview

SmartDV’s Interlaken Synthesizable Transactor is a fully featured Interlaken chip-to-chip interconnect bus model purpose-built for hardware emulation and FPGA prototyping environments requiring fast, accurate, and highly configurable Interlaken TX and RX behavior during pre-silicon validation of high-bandwidth networking, data center, and AI interconnect designs. Fully compliant with Interlaken Protocol v1.2, Interlaken Look-Aside Protocol v1.0, Interlaken Retransmission Extension v1.1, and Interlaken Interoperability Recommendations v1.3 and v1.4, it delivers complete TX BFM and RX BFM functionality with configurable multi-channel and multi-lane support, giving validation teams a drop-in synthesizable Interlaken transactor ready for rapid integration into emulation and prototyping flows.

Designed for the speed and visibility demands of emulation and FPGA prototyping rather than ASIC tape-out, the transactor emphasizes fast bring-up, fine-grained controllability, and on-the-fly protocol checking over area or power optimization. It supports configurable burst max, burst short, and metaframe lengths, per-channel inband and out-of-band flow control, scheduling calendar logic with optional decision algorithm for bandwidth optimization, burst control word encapsulation, per-lane CRC-32 insertion, configurable scrambler, 64B/67B encoding, and flexible SerDes interface widths, enabling validation teams to exercise corner-case Interlaken behavior that is difficult to reach with production RTL alone.

Built for fast compile times and efficient resource utilization on hardware emulation and FPGA prototyping platforms, the transactor is fully synthesizable and platform-independent, deploying without modification across any major emulation or prototyping environment. Its comprehensive PRBS and user-defined test pattern generation and checking, extensive error injection suite, and rich set of configuration parameters controlling Interlaken functionality enable rapid deployment for early software bring-up and system-level validation regardless of the underlying emulation platform.

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Interlaken Transactor
Benefits
  • Full Interlaken TX and RX BFMComplete Interlaken TX BFM and RX BFM per Interlaken Protocol v1.2 with configurable multi-channel and multi-lane support
  • Flexible Lane and Burst Configuration – Configurable number of serial lanes, burst max and burst short sizes, extra idle insertion for burst short avoidance, and configurable metaframe length
  • Scheduling and Flow Control – Scheduling calendar logic with optional decision algorithm for unused bandwidth avoidance and per-channel inband, out-of-band, or combined flow control
  • 64B/67B Encoding and Scrambler64B/67B encoding with controllable inversion bits and configurable scrambler enable/disable for flexible signal integrity validation
  • Flexible SerDes Interface – 32, 20, 16, 10, and 8-bit SerDes interface bus widths plus 67-bit bus per lane and 1-bit serial lane for ease of debug
  • Per-Lane CRC and Skew InsertionPer-lane CRC-32 insertion into diagnostic words and per-lane skew insertion for comprehensive lane alignment validation
  • Test Pattern Generation and Checking – PRBS31, PRBS23, PRBS7, and user-defined pattern generation and checking for physical layer validation
  • Comprehensive Error InjectionSerDes lock loss, word boundary sync loss, bad scrambler state, lane alignment failure, burst CRC24 errors, flow control errors, unknown control word types, bad 64B/67B codewords, diagnostic CRC32 errors, metaframe errors, short burst errors, invalid burst boundary, and test pattern errors
  • On-the-Fly Protocol CheckingReal-time protocol and data checking with testbench notification of significant events, warnings, timing, and protocol violations
Compliance and Compatibility
  • Fully compliant with Interlaken Protocol Definition v1.2
  • Compliant with Interlaken Look-Aside Protocol Specification v1.0
  • Compliant with Interlaken Retransmission Extension Specification v1.1
  • Compliant with Interlaken Interoperability Recommendations v1.3 and v1.4
  • Fully synthesizable and platform-independent, deployable on any hardware emulation or FPGA prototyping platform
  • Vendor-agnostic integration suitable for Synopsys, Cadence, Siemens, and custom emulation and prototyping environments
  • Configurable interface supporting integration into custom emulation and prototyping testbenches

Request Datasheet