SmartDV’s FPD-Link Verification IP is a comprehensive solution for verifying Texas Instruments FPD-Link serializer/deserializer interfaces, the automotive industry’s dominant SerDes technology for transmitting uncompressed video, control data, and power over a single low-latency cable between ADAS cameras, radar sensors, LiDAR modules, and display panels in automotive systems. Compliant with FPD-Link IV (2024) and backward compatible with FPD-Link III, II, and I, it supports complete verification of FPD-Link Source and Device components across 8 serial data lines and two clock lines, DC balanced and unbalanced operation, all RGB pixel formats from 18-bit to 24-bit single and dual pixel, DDC2B protocol for EDID retrieval, High-Bandwidth Digital Content Protection v1.3, and EDID 1.3 and 2.0 data structures.
SmartDV’s FPD-Link VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With intra-pair and inter-pair skew insertion and detection, all standard display resolutions from 640×480 through 2048×1536, user-controlled default configuration, rich configuration parameter set, error injection and detection, built-in functional coverage, and a complete test suite, SmartDV’s FPD-Link VIP enables verification teams to thoroughly validate FPD-Link interface designs for automotive surround-view camera systems, ADAS sensor hubs, digital cockpit display controllers, autonomous vehicle perception systems, and any automotive application requiring high-bandwidth, low-latency uncompressed video SerDes.
