Fibre Channel VIP

Simulation

Benefits Compliance and Compatibility Request a Datasheet

Overview

SmartDV’s Fibre Channel Verification IP is a comprehensive solution for verifying the Fibre Channel high-speed serial storage network interface, the dominant enterprise storage area network protocol enabling deterministic, lossless fabric connectivity between servers, storage arrays, and tape libraries. Fully compliant with FC-FS-6, FC-LS-4, FC-PI-7, and FCP-4, and conformant with SCSI Architecture Models SAM-3, SAM-4, and SAM-5, it supports complete verification of Fibre Channel Initiator and Target components across all defined interface widths, 8B/10B, 64B/66B, and 256B/257B encoding, all speeds from 1GFC through 256GFC including 128GFC Gen 8, and all FC port types including L, N, and F ports.

SmartDV’s Fibre Channel VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With complete port, process, and fabric login/logout, transmitter training, Forward Error Correction, Energy Efficient Fibre Channel, all SCSI commands, multiple outstanding exchanges, multiple LUN addressing, configurable target discovery, error detection and recovery, comprehensive error injection at all layers, built-in functional coverage, and a complete test suite, SmartDV’s Fibre Channel VIP enables verification teams to thoroughly validate Fibre Channel interface designs for enterprise HBAs, FC switches and directors, storage array controllers, and any enterprise SAN infrastructure requiring high-performance, lossless block storage connectivity.

Request Data Sheet

Benefits

Full FC Initiator and Target Support – Provides complete Fibre Channel Initiator and Target component verification across 1-bit serial and 8/10/20/32/40/64-bit parallel interfaces, 8B/10B, 64B/66B, and 256B/257B encoder/decoder interfaces, 32-bit Dword Primitive interface, Dword-level transport interface, and complete Frame transaction level interface, supporting multiple initiators and multiple targets.
Comprehensive Speed Coverage – Supports all defined Fibre Channel speeds including 1GFC, 2GFC, 4GFC, 8GFC, 16GFC, 32GFC, 64GFC, 128GFC, and 256GFC with speed switching and negotiation, transmitter training, Forward Error Correction, and Energy Efficient Fibre Channel for complete generational coverage through Gen 8.
Protocol Layer and Port Coverage – Supports L ports for arbitrated loop topology, N ports for point-to-point and fabric connectivity, and F ports for fabric switch connectivity, with Port Login, Process Login, Fabric Login, and all corresponding Logout sequences, and completely configurable target and device discovery.
SCSI Command and Exchange Coverage – Supports all SCSI commands per FCP-4 and SAM-3/4/5, multiple outstanding exchanges, several queuing attribute models, multiple Logical Unit Number addressing, generation of all FC frame types, verification of all Fibre Channel protocol layers, error detection and recovery management, retry control, and all defined FC timers.
Comprehensive Error Injection and Detection – Supports error injection and detection at each protocol layer including invalid frame fields, invalid EOF and SOF, oversize and undersize frames, disparity errors, invalid code group errors, invalid K and D characters, and CRC errors, with proficiency to generate random frames and respond in directed or randomized fashion.
Complete Verification Infrastructure – Provides a full test suite covering all FC-FS-6, FC-LS-4, FC-PI-7, and FCP-4 specification features, built-in functional coverage analysis, constraints randomization, status counters for bus events, and callbacks in Initiator, Target, and Monitor for user-defined event handling and protocol and timing violation notification.

Compliance and Compatibility

Fully compliant with FC-FS-6 (Rev 0.1), FC-LS-4 (Rev 4.03), FC-PI-7 (Rev 0.13), and FCP-4
Conformant with SCSI Architecture Models SAM-3, SAM-4, and SAM-5
Supports all FC speeds from 1GFC through 256GFC including 128GFC Gen 8
Supports 8B/10B, 64B/66B, and 256B/257B encoding with Forward Error Correction
Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

Request Datasheet