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eUSB VIP

Simulation
Key Features Compliance and Compatibility Request a Datasheet
Overview

SmartDV’s USB 2.x OTG IP is a silicon-proven, fully featured Universal Serial Bus On-The-Go solution purpose-built for SoC designs requiring flexible, dual-role USB connectivity across mobile, automotive, IoT, and consumer electronics applications. Fully compliant with USB 2.0, USB OTG and Embedded Host Revision 2.0, and USB OTG EH3 Revision 1.0, it delivers a comprehensive USB OTG implementation available in USB 2.0 Embedded Host, USB 2.0 Peripheral Only, and USB 2.0 OTG configurations — supporting High Speed, Full Speed, and Low Speed operation with xHCI-compliant host mode operation at up to 480 Mbps.

Designed to address the full breadth of USB 2.x OTG integration requirements, the IP supports Session Request Protocol (SRP), Host Negotiation Protocol (HNP), and Attach Detach Protocol (ADP) for complete OTG role switching, alongside a proprietary DMA engine for high-efficiency data transfer, configurable endpoint management, 32-bit and 64-bit internal and AXI data paths, and comprehensive root hub features for Embedded Host applications. Its software-configurable speed and HNP/ADP support, optional simple slave mode for area-optimized designs, all USB Link Power Management states L1 and L2, and system power management give SoC teams a production-tested, feature-complete USB 2.x OTG implementation suited for the most demanding mobile and embedded dual-role USB designs.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its 16-bit UTMI+ Level 3 PHY interface, AXI DMA path, AHB register path, and configurable endpoint architecture enable fast integration and confident design bring-up across a wide range of process nodes and target applications.

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eUSB VIP
Key Features
  • Full eUSB2 Host and Peripheral Support – Provides complete eUSB2 Host and Peripheral component verification in native mode and repeater architecture mode, supporting high-speed low-voltage differential signaling and low-speed and full-speed single-ended digital low-voltage signaling, selected single speed configuration in native mode, and dual-role repeater operation.
  • eUSB2 Rev 1.2 Feature Coverage – Supports all features defined in eUSB2 Rev 1.2 including Repeater HS SYNC Forward and Native Mode Auto-Resume ECNs published September 2024, link power management LPM-L1 and Suspend (L2), register access protocol for eUSB2 device and repeater configurations, and full USB 2.0 protocol layer compliance.
  • eUSB2V2 High-Speed Link Support – Supports eUSB2V2 data rates up to 4.8 Gbps including HS1 at 480 Mbps, HS2 at 960 Mbps, and higher symmetric rates up to 4.8 Gbps, asymmetric link configurations with 4.8 Gbps downstream and 480 Mbps upstream, symmetric link configurations from 960 Mbps to 4.8 Gbps, UTMI 2.0 interface, and native mode only operation as defined in the eUSB2V2 specification.
  • USB 2.0 Protocol Layer Compliance – Supports all USB 2.0 transfer types including Control, Isochronous, Interrupt, and Bulk, transaction-level and packet-level transmission and reception, all descriptor types and device requests, bus enumeration, SOF generation, auto detection of device connection and disconnection, and programmable inter-packet and end-to-end delays.
  • Link Power Management and Register Access Protocol – Supports LPM-L1 link power management and Suspend (L2) power states, register access protocol for eUSB2 device and repeater configuration, PHY state transitions and power management, disconnect detection, and port reset and configuration sequences in native mode.
  • Comprehensive Error Injection and Detection – Supports injection and detection of all USB error types including corrupt Sync byte, corrupt PID byte, corrupt CRC-5 and CRC-16, corrupt endpoint address byte, corrupt Setup payload size and data payload, corrupt EOP byte, and bit stuffing errors, with on-the-fly protocol and data checking across all eUSB2 operating modes.
  • Complete Verification Infrastructure – Provides a full test suite covering all eUSB2 Rev 1.2 and eUSB2V2 specification features, built-in functional coverage analysis, constraints randomization, status counters for bus events, and callbacks in Host, Device, and Monitor for user-defined event handling and protocol and timing violation notification.
Compliance and Compatibility
  • Fully compliant with eUSB2 Physical Layer Supplement to USB Revision 2.0 Specification Rev 1.2 (September 2024)
  • Fully compliant with eUSB2V2 Supplement to USB 2.0 Specification (September 2024)
  • Supports eUSB2V2 data rates up to 4.8 Gbps in symmetric and asymmetric link configurations
  • Compliant with USB Revision 2.0 Specification at the protocol layer
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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