Ethernet 25G TSN MAC IP

Design IP

Overview

SmartDV’s Ethernet 25G TSN (Time-Sensitive Networking) MAC IP Core brings together the precision of IEEE TSN standards and the speed of 25G Ethernet to address the needs of latency-sensitive and synchronized communication. It is ideal for industrial automation, automotive systems, and edge computing applications requiring deterministic behavior over Ethernet.

Compliant with IEEE 802.3by and TSN standards such as 802.1Qbv (time-aware shaping), 802.1Qbu/802.3br (frame preemption), and 802.1AS (time synchronization), the IP core supports VLAN tagging, traffic prioritization, and QoS enforcement. The MAC interfaces with PCS layers via XGMII or USXGMII and supports robust traffic management features for real-time applications.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance.

Benefits

Deterministic 25G Ethernet Operation – Fully compliant with IEEE 802.3-2022 and Time-Sensitive Networking (TSN) standards to deliver predictable, low-latency Ethernet communication at 25 Gbps
Integrated TSN Capabilities – Implements IEEE 802.1Qbv Time-Aware Shaper (TAS), 802.1Qav Credit-Based Shaper (CBS), 802.1AS for precise time synchronization, and 802.1Qci for per-stream filtering and policing
Multi-Speed Operation – Configurable for operation at 10 G / 5 G / 2.5 G / 1 G speeds, ensuring backward compatibility and seamless integration into mixed-rate TSN environments
Flexible Interface Options – Supports CGMII, XGMII, and AXI-Stream interfaces for versatile connectivity between controllers, PHYs, and SoCs
Precision Time Control – Enables accurate timestamping, gated transmission scheduling, and per-stream shaping to ensure deterministic traffic delivery
Advanced Frame Management – Supports jumbo frames, VLAN tagging (IEEE 802.1Q/802.1ad), CRC/FCS generation and checking, control and pause frames, and programmable inter-packet gap
Seamless PCS Integration – Designed to integrate directly with SmartDV 25G PCS IP, providing a fully verified TSN-compliant MAC-to-PHY pipeline for ASIC and FPGA designs

Compliance and Compatibility

Fully compliant with IEEE 802.3-2022 and Time-Sensitive Networking standards
Supports TSN profiles defined in IEEE 802.1Qbv, 802.1Qav, 802.1AS, and 802.1Qci
Compatible with CGMII, XGMII, and AXI-Stream interfaces
Compatible with all major EDA synthesis, simulation, and linting flows

Related Products

Ethernet 25G MAC IP

Ethernet 25G PCS IP

Ethernet – Up to 800G VIP