SmartDV’s DMA Controller with AXI IP is a silicon-proven, fully featured Direct Memory Access solution purpose-built for SoC designs requiring efficient, autonomous data transfer across AI/ML accelerator, automotive, and high-performance computing subsystem designs. Supporting the latest ARM AMBA AXI5 and backward compatible with AXI3/4, AXI4-Lite, ACE, ACE-Lite, and AXI4-Stream specifications, it delivers 1 to 16 channel DMA transmit and receive engines with AXI Master and Slave bus support, ring and chained descriptor structure access, and full duplex operation processing read and write transfers simultaneously.
Designed for the practical integration requirements of modern high-performance SoC designs, the IP supports memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral DMA transfers, sideband DMA request and grant triggering, scatter-gather lists, 8/16/32/64/128/256-bit wide data transfers, configurable QoS per channel, programmable burst capability, and link-list based processor for autonomous operation. Its configurable transmit and receive engine sized to host memory data width, configurable endianness, round-robin channel arbitration, per-channel interrupt output, and support for up to 64 MB transfer per Buffer Descriptor give SoC teams a production-tested, feature-complete AXI DMA controller.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized channel count and configurable interface widths enable fast integration across a wide range of process nodes and target applications.
