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Camera Parallel Interface (CPI) Receiver IP
Design IP
Overview

SmartDV’s Camera Parallel Interface (CPI) Receiver IP is a high-performance solution designed to interface image sensors with SoCs or FPGAs in a range of embedded vision, surveillance, and imaging applications. It enables efficient capture of parallel video data streams, supporting various pixel formats and synchronization schemes to ensure reliable and accurate data transfer.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. With support for industry-standard interfaces and compatibility with popular image sensors, the CPI Receiver IP simplifies integration and accelerates time-to-market for camera-enabled systems.

Benefits
  • Flexible Sensor Connectivity – Enables seamless interfacing with image sensors following the CPI OV7670 v1.0 standard
  • Configurable Data Bus Support – Supports 8-bit to 14-bit input formats and common color encodings including RGB444, RGB555, and RGB565
  • Robust Synchronization Support – Handles VSYNC, HSYNC, and PCLK signals to ensure reliable frame and line-level synchronization
  • High-Speed Video Capture – Optimized for efficient reception and packing of video data across supported CPI formats
  • Programmable Control Interface – Includes device control register set as defined in CPI OV7670 v1.0 for sensor-level configuration
Compliance and Compatibility
  • Fully compliant with CPI OV7670 v1.0 specification, including supported color formats and register map
  • Compatible with popular CMOS image sensors and industry-standard CPI implementations
  • Compatible with all major EDA synthesis, simulation, and linting flows