SmartDV’s CAN Verification IP is a comprehensive solution for verifying Controller Area Network designs across CAN 2.0, CAN with Flexible Data Rate, and Time-Triggered CAN implementations. Fully compliant with ISO 11898-1:2024 for the data link layer and physical coding sublayer and ISO 11898-4:2004 for Time-Triggered CAN, and adherent to CAN 2.0 Part A and Part B specifications, it supports complete verification of CAN TX and RX node functionality in full duplex operation across all frame types, error types, and conformance test cases as defined in ISO/DIS 16845.
SmartDV’s CAN VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With TEC/REC error counter and fault state tracking, glitch injection and detection, automatic remote frame handling, re-transmission of corrupted messages, constraints randomization, built-in functional coverage, and a complete test suite, SmartDV’s CAN VIP enables verification teams to thoroughly validate automotive, industrial, and embedded CAN bus designs for automotive ECUs, ADAS, industrial automation, and safety-critical networked control applications.
