SmartDV’s CAN Verification IP is built to validate controller area network protocols in automotive and industrial SoC designs through simulation. Fully compliant with ISO 11898 standards, it enables accurate and efficient verification of classical CAN, CAN FD, and CAN with Time Triggered (TT) extensions.

The VIP supports major verification languages, including SystemVerilog and Verilog, and integrates seamlessly with methodologies such as UVM, OVM, and VMM. It is simulator-independent and compatible with all leading EDA vendors’ simulators, ensuring broad usability across verification environments.

With configurable node behavior, integrated protocol checkers, error injection capabilities, and coverage metrics, SmartDV’s CAN VIP accelerates testbench development and ensures protocol compliance. It enables verification teams to confidently validate reliable in-vehicle communication and real-time control systems across automotive, industrial automation, and robotics applications.